Matching of figures of merit (FOMs) in MOS transistors can be an important design parameter in many analog CMOS applications. Such matching involves statistical differences between pairs of identically-designed and nominally identically-used transistors. In analog circuit blocks, like A/D converters, threshold voltage differences as small as one millivolt or less between transistors in a matched set can be sufficient to adversely impact the performance and/or yield of a product employing the transistors.
Typical MOS transistors include a polysilicon gate electrode over a gate dielectric layer. Polysilicon includes grain boundaries along which dopant atoms may preferentially diffuse. Such diffusion may cause dopant atoms to concentrate at the interface between the gate electrode and the gate dielectric. Moreover, the dopant atoms may be further concentrated at the intersections of the grain boundaries and the interface between the gate electrode and the gate dielectric. The localized concentrations of dopant atoms may adversely impact the stability and matching of various transistor FOMs, thereby constraining the design of an electronic device of which the transistors are a part.